1. Field of the Invention
The present invention relates to a high-speed data transceiver device, and more particularly, to a high-speed interface operating at a quadrature data rate (QDR) and a method thereof, optimally suited implementation in semiconductor memories.
2. Description of the Related Art
To increase a data transmission speed of semiconductor devices, a method of transmitting two or more bits (or symbols) of data per data pin (or bus) during a single clock cycle is widely used. An example is a double data rate (DDR) dynamic random access memory (DRAM). To achieve a higher data transmission rate than a DDR, recently, a quadrature data rate (QDR) method has been introduced.
FIGS. 1A and 1B are conceptual diagrams of a DDR transmission mode and a QDR transmission mode, respectively. Referring to FIG. 1A, a strobe signal DQS is used to transmit data in the DDR mode. In the DDR mode, a controller or a memory uses rising edges and falling edges of the strobe signal DQS when transmitting data DQ's. In addition, the rising edges and the falling edges of the strobe signal DQS are used to detect the data DQ's.
When the DDR mode is used, the data DQ's can be transmitted two times faster than the frequency of the strobe signal DQS. In other words, when the DDR mode is used, a data transmission speed two times higher than a frequency of a clock signal CLK can be achieved. Meanwhile, in semiconductor systems having a data transmission speed of several gigabytes per second or higher, the frequency of the strobe signal DQS should be several gigahertz. However, when the frequency of the strobe signal DQS is several gigahertz, it is difficult to distribute the strobe signal DQS on a chip and to operate a sampling circuit detecting the data DQ's. Accordingly, to overcome these problems, the QDR mode illustrated in FIG. 1B is used.
When the QDR mode is used, a data transmission speed four times higher than a frequency of a clock signal CLK can be achieved. In the QDR mode, rising edges and falling edges of two strobe signals DQS_0 and DQS_90 having a phase of 0 degrees and a phase of 90 degrees, respectively, are used to transmit data DQ's. Accordingly, a device for transmitting the data DQ's and a device for receiving the data DQ's need the two strobe signals DQS_0 and DQS_90.
FIG. 2 is a schematic block diagram of a conventional QDR transceiver semiconductor device including a QDR transmitter semiconductor device 200 and a QDR receiver semiconductor device 250. A QDR transmitter semiconductor device 200 (e.g., part of a memory controller) includes a data transmission circuit 210, a phase-locked loop (PLL) 220, and a strobe signal transmitter 230. The transmitter semiconductor device 200 generates two clock signals DQS_0 and DQS_90 having a phase difference of 90 degrees using the PLL 220. The data transmission circuit 210 transmits data DQ's using the two clock signals DQS_0 and DQS_90 generated by the PLL 220. The strobe signal transmitter 230 transmits one clock signal DQS among the two clock signals DQS_0 and DQS_90 generated by the PLL 220 to a receiver semiconductor device 250.
The receiver semiconductor device 250 (e.g., part of a memory device) includes a data reception circuit 260, a strobe buffer 270, and a delay-locked loop (DLL)/PLL 280. The strobe buffer 270 receives the strobe signal DQS from the transmitter semiconductor device 200 and buffers it. The DLL/PLL 280 generates an internal clock signal DQS_0′ synchronized with the strobe signal DQS and an internal clock signal DQS_90′ having a phase difference of 90 degrees with respect to the strobe signal DQS (or with DQS_0). The data reception circuit 260 receives the data DQ's using the two internal clock signals DQS_0′ and DQS_90′ output from the DLL/PLL 280.
As described above, in a conventional QDR mode, the receiver semiconductor device 250 requires the PLL or DLL 280 that can generate the clock signals DQS_0′ and DQS_90′ having a phase difference of 90 degrees. In this case, circuit area and power consumption is significant. Moreover, since the internal clock signals DQS_0′ and DQS_90′ are generated using the PLL or DLL 280, phase jitter may occur due to the characteristics of the PLL or DLL 280, as illustrated in (the signal DQS_90) in FIG. 1B. Furthermore, since a path difference occurs between the data DQ's and each of the clock signals DQS_0′ and DQS_90′, phase noise tracking is difficult.